verilog

Verilog HDL Program for Carry Save Adder

Simulated waveform for Carry Save Adder

Verilog HDL Program for Carry Save Adder. 1 2 3 4 5 6 7 8 9 10 11 12 13 module carrysave(s,c,a,b); output [3:0]s; output c; input [3:0]a,b; wire [2:0]c2,c0; fa u1(s[0],c0[0],a[0],b[0],1′b0); dff1 u2(c2[0],c0[0],clk); fa u3(s[1],c0[1],a[1],b[1],c2[0]); dff1 u4(c2[1],c0[1],clk); fa u5(s[2],c0[2],a[2],b[2],c2[1]); dff1 u6(c2[2],c0[2],clk); fa u7(s[3],c,a[3],b[3],c2[2]); endmodule

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Verilog HDL Program for Serail In – Parallel Out Shift Register

Simulated Waveform for Serail In – Parallel Out Shift Register

Verilog HDL Program for Serail In – Parallel Out Shift Register. 1 2 3 4 5 6 7 8 module sipo(sout,sin,clk); output [3:0]sout; input sin,clk; dff2 u1(sout[0],sin,clk); dff2 u2(sout[1],sout[0],clk); dff2 u3(sout[2],sout[1],clk); dff2 u4(sout[3],sout[2],clk); endmodule

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Verilog HDL Program for Parallel In – Parallel Out Shift Register

Simulated Waveform for Parallel In – Parallel Out Shift Register

Verilog HDL Program for Parallel In – Parallel Out Shift Register 1 2 3 4 5 6 7 8 9 module pipo(sout,sin,clk); output [3:0]sout; input [3:0]sin; input clk; dff1 u1(sout[0],sin[0],clk); dff1 u2(sout[1],sin[1],clk); dff1 u3(sout[2],sin[2],clk); dff1 u4(sout[3],sin[3],clk); endmodule

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Verilog HDL Program for Parallel In – Serial Out Shift Register

Simulated Waveform for Parallel In – Serial Out Shift Register

Verilog HDL Program for Parallel In – Serial Out Shift Register. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module piso1(sout,sin,clk); output sout; input [3:0]sin; input clk; wire [3:0]q; inv u1(p,sl); and1 u2(n,sin[1],p); and1 u3(r,sl,q[0]); or1 u4(s,n,r); and1 u5(t,sin[2],p); and1 u6(u,sl,q[1]); or1 […]

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Verilog HDL Program for BCD to GRAY conversion

Simulated Waveform for BCD to GRAY conversion

Verilog HDL Program for BCD to GRAY conversion. 1 2 3 4 5 6 7 8 9 10 11 module bcd2gray(o,i); output [2:0]o; input [2:0]i; reg [2:0]o; always @(i) begin o[2]=i[2]; o[1]=i[2]^i[1]; o[0]=i[1]^i[0]; end endmodule

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Verilog HDL Program for J K Flip Flop

Simulated waveform for J-K Flip Flop

A flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and […]

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Verilog HDL Program for 3-8 ENCODER

Simulated waveform for 3-8 Encoder

An encoder is a device, circuit, transducer, software program, algorithm or person that converts information from one format or code to another, for the purposes of standardization, speed, secrecy, security, or saving space by shrinking size. 1 2 3 4 5 6 7 8 9 10 11 12 13 module encoder83(o,i); output [2:0]o; input [7:0]i; […]

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Verilog HDL Program for EXCLUSIVE NOR Logic Gate

Simulated waveform for Ex-nor Gate

The XNOR gate is a digital logic gate whose function is the inverse of the exclusive OR (XOR) gate. A HIGH output (1) results if both of the inputs to the gate are the same. If one but not both inputs are HIGH (1), a LOW output (0) results. 1 2 3 4 5 6 […]

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Verilog HDL Program for EXCLUSIVE OR Logic Gate

Simulated waveform for Ex-or Gate

The XOR gate is a digital logic gate that implements an exclusive or; that is, a true output (1) results if one, and only one, of the inputs to the gate is true (1). If both inputs are false (0) or both are true (1), a false output (0) results. A way to remember XOR […]

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