Verilog HDL Program for Decade Counter

Simulated Waveform for Decade Counter Saturday, June 9th, 2012  »  Posted By  »  Total 0 Comment

Verilog HDL Program for Decade Counter. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 module mod10(qo,clk); output [3:0]qo; input clk; inv u1(qc,q3); inv u2(qb,q1); inv u3(qa,q0); and1 u4(j3,q1,q0,q2); assign k3=q0; and1 u5(k2,q1,q0); assign j2=k2; and1 u6(j1,qc,q0); assign k1=q0; assign j0=1′b1; assign k0=1′b1; jk1 […]

Verilog HDL Program for Mod-13 Counter

Simulated Waveform for Mod-13 Counter Saturday, June 9th, 2012  »  Posted By  »  Total 0 Comment

Verilog HDL Program for Mod-13 Counter. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 module mod13(qo,clk); output [3:0]qo; input clk; inv u1 (qd,q3); inv u2(qc,q2); and1 u3 (a,q1,q0,q2); and1 u4(b,q3,q2); or1 u5(t3,a,b); and1 u6(c,q1,q0); and1 u7(d,q3,q2); or1 u8(t2,c,d); assign t1=q0; or1 u9(t0,qd,qc); tff u10(qo[0],t0,clk); […]

Verilog HDL Program for Johnson Counter

Simulated Waveform for Johnson Counter Saturday, June 9th, 2012  »  Posted By  »  Total 0 Comment

Verilog HDL Program for Johnson Counter. 1 2 3 4 5 6 7 8 9 module johnson(q,clk); output [3:0]q; input clk; not (qc,q[0]); dff u1(q[3],qc,clk); dff1 u2(q[2],q[3],clk); dff1 u3(q[1],q[2],clk); dff1 u4(q[0],q[1],clk); endmodule

Verilog HDL Program for Serail In – Serial Out Shift Register

Simulated Waveform for Serail In – Serial Out Shift Register Saturday, June 9th, 2012  »  Posted By  »  Total 0 Comment

Verilog HDL Program for Serail In – Serial Out Shift Register. 1 2 3 4 5 6 7 8 module sipo(sout,sin,clk); output [3:0]sout; input sin,clk; dff2 u1(sout[0],sin,clk); dff2 u2(sout[1],sout[0],clk); dff2 u3(sout[2],sout[1],clk); dff2 u4(sout[3],sout[2],clk); endmodule

Verilog HDL Program for T flip flop using RS flip flop

Simulated Waveform for T flip flop using RS flip flop Saturday, June 9th, 2012  »  Posted By  »  Total 0 Comment

Verilog HDL Program for T flip flop using RS flip flop. 1 2 3 4 5 6 7 8 module sr2t(q,q1,t,clk); output q,q1; input t,clk; wire x,y; and1 u1(x,t,q1); and1 u2(y,t,q); srff u3(q,q1,y,x,clk); //srff u(q,q1,r,s,clk); endmodule

Verilog HDL Program for JK flip flop using RS flip flop

Simulated Waveform for JK flip flop using RS flip flop Saturday, June 9th, 2012  »  Posted By  »  Total 0 Comment

VHDL Program for JK flip flop using RS flip flop. 1 2 3 4 5 6 7 8 module sr2jk(q,q1,j,k,clk); output q,q1; input j,k,clk; and1 u1(w,j,q1); inv u4(k1,k); and1 u2(x,k1,q); srff u3(q,q1,x,w,clk); endmodule

Verilog HDL Program for T Flip Flop

Simulated Wave form for Toggle flip flop Saturday, June 9th, 2012  »  Posted By  »  Total 0 Comment

A flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and […]

Verilog HDL Program for D Flip Flop

Simulated waveform for D Flip Flop Saturday, June 9th, 2012  »  Posted By  »  Total 1 Comment

A flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and […]

Verilog HDL Program for R-S Flip Flops

RS Flip Flop Saturday, June 9th, 2012  »  Posted By  »  Total 0 Comment

A flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and […]

Verilog HDL Program for BCD Adder using Parallel Adder

Simulated waveform for BCD Adder Saturday, June 9th, 2012  »  Posted By  »  Total 0 Comment

VHDL Program for BCD Adder using Parallel Adder. 1 2 3 4 5 6 7 8 9 10 11 12 13 module bcdas(s,c,a,b); output [3:0]s; output c; input [3:0]a,b; wire [3:0]x; wire z,y,co,c1,k; parad4 u1(x,c1,a,b); and1 u2(y,x[3],x[2]); and1 u3(z,x[1],x[3]); or1 u4(k,z,y); or1 u5(c,k,c1); parad4 u6(s,co,x,{1′b0,c,c,1′b0}); endmodule

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