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Verilog HDL Program for Random Number Generator

Simulated waveform for Random Number Generator Saturday, June 9th, 2012  »  Posted By  »  Total 0 Comment

Verilog HDL Program for Random Number Generator. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 module tff(q,t,c); output q; input t,c; reg [...]

Verilog HDL Program for the function f=x>>3 + x<<4

Simulated waveform for the function f=x>>3 + x Saturday, June 9th, 2012  »  Posted By  »  Total 0 Comment

Verilog HDL Program for the function f=x>>3 + x

Verilog HDL Program for Ring Counter

Simulated Waveform for Ring Counter Saturday, June 9th, 2012  »  Posted By  »  Total 3 Comments

Verilog HDL Program for Ring Counter. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 module dff(q,d,c); output q; input d,c; reg q; initial q=1′b1; always @ (posedge c) q=d; endmodule   module dff1(q,d,clk); output q; [...]

Verilog HDL Program for 3-8 DECODER USING 2-4 DECODER

Simulated waveform for 3-8 Decoder Saturday, June 2nd, 2012  »  Posted By  »  Total 1 Comment

A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. It is a combinational circuit that converts binary information from n input lines to a maximum of [...]

Verilog HDL program for 4-BIT Parallel Adder

Simulated waveform for Parallel Adder Saturday, June 2nd, 2012  »  Posted By  »  Total 0 Comment

A 4 bit binary parallel adder can be formed by cascading four full adder units. The carry of each stage is connected to the next unit as the carry in (That is the third input). 1 2 3 4 5 6 7 8 9 10 module parad4(a,c,p,q); output [3:0]a; output c; input [3:0]p,q; wire c1,c2,c3; [...]

Verilog HDL Program for HALF ADDER

Half Adder Thursday, May 31st, 2012  »  Posted By  »  Total 0 Comment

The half adder adds two one-bit binary numbers A and B. It has two outputs, S and C (the value theoretically carried on to the next addition); the final sum is 2C + S. The simplest half-adder design, pictured on below, incorporates an XOR gate for S and an AND gate for C. With the [...]

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