Verilog lab

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Verilog HDL Program for JK flip flop using RS flip flop

VHDL Program for JK flip flop using RS flip flop. 1 2 3 4 5 6 7 8 module sr2jk(q,q1,j,k,clk); output q,q1; input j,k,clk; and1 u1(w,j,q1); inv u4(k1,k); and1 u2(x,k1,q); srff u3(q,q1,x,w,clk); endmodule

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Verilog HDL Program for R-S Flip Flops

A flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and […]