Shift Register

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Verilog HDL Program for Serail In – Parallel Out Shift Register

Verilog HDL Program for Serail In – Parallel Out Shift Register. 1 2 3 4 5 6 7 8 module sipo(sout,sin,clk); output [3:0]sout; input sin,clk; dff2 u1(sout[0],sin,clk); dff2 u2(sout[1],sout[0],clk); dff2 u3(sout[2],sout[1],clk); dff2 u4(sout[3],sout[2],clk); endmodule

556 Comments

Verilog HDL Program for Parallel In – Parallel Out Shift Register

Verilog HDL Program for Parallel In – Parallel Out Shift Register 1 2 3 4 5 6 7 8 9 module pipo(sout,sin,clk); output [3:0]sout; input [3:0]sin; input clk; dff1 u1(sout[0],sin[0],clk); dff1 u2(sout[1],sin[1],clk); dff1 u3(sout[2],sin[2],clk); dff1 u4(sout[3],sin[3],clk); endmodule

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Verilog HDL Program for Parallel In – Serial Out Shift Register

Verilog HDL Program for Parallel In – Serial Out Shift Register. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module piso1(sout,sin,clk); output sout; input [3:0]sin; input clk; wire [3:0]q; inv u1(p,sl); and1 u2(n,sin[1],p); and1 u3(r,sl,q[0]); or1 u4(s,n,r); and1 u5(t,sin[2],p); and1 u6(u,sl,q[1]); or1 […]