prime number

1 Comment

Verilog HDL Program for detecting whether a given number is Prime or not

Verilog HDL Program for detecting whether a given number is Prime or not. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 module primenum3(o,i); output o; input [10:0]i; integer k; reg o; always @(i) begin k=i; if(i[0]==1’b0) begin o=1’b0; $display("not prime"); end else begin […]