Verilog HDL program for Inverter Logic gate

Thursday, May 31st, 2012

In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. An inverter circuit outputs a voltage representing the opposite logic-level to its input.

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module inv(o,a);
    output o;
    input a;
    assign o=!a;
endmodule
Simulated waveform for Inverter

Simulated waveform for Inverter

Author Name :
Ansten Lobo

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