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Verilog HDL Program for Serail In – Parallel Out Shift Register

Saturday, June 9th, 2012

Verilog HDL Program for Serail In – Parallel Out Shift Register.

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module sipo(sout,sin,clk);
    output [3:0]sout;
    input sin,clk;
    dff2 u1(sout[0],sin,clk);
    dff2 u2(sout[1],sout[0],clk);
    dff2 u3(sout[2],sout[1],clk);
    dff2 u4(sout[3],sout[2],clk);
endmodule
Simulated Waveform for Serail In – Parallel Out Shift Register

Simulated Waveform for Serail In – Parallel Out Shift Register

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