Verilog HDL Program for Ring Counter

Verilog HDL Program for Ring Counter.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
module dff(q,d,c);
    output q;
    input d,c;
    reg q;
    initial   
     q=1'b1; 
    always @ (posedge c)
       q=d;
    endmodule
 
module dff1(q,d,clk);
    output q;
    input d,clk;
    reg q;
    initial 
    q=1'b0;
    always @ (posedge clk)
    q=d;
endmodule
 
module ring(q,clk);
    inout [3:0]q;
    input clk;
    dff u1(q[0],q[3],clk);
    dff1 u2(q[1],q[0],clk);
    dff1 u3(q[2],q[1],clk);
    dff1 u4(q[3],q[2],clk);
endmodule
Simulated Waveform for Ring Counter
Simulated Waveform for Ring Counter

7 Responses to “Verilog HDL Program for Ring Counter”

  1. HI,
    I want johnson’s ringcounter VHDL code&block diagram&circut diagram.please send this info to my mail quickly.

    Reply
  2. i want verilog code for johnson ring counter and 2bit,4bit ring counter reply it to me on mail

    Reply
  3. i want verilog code for johnson ring counter and as well as 2 bit, 4 bit ring counter reply it to me on mail

    Reply

Leave a Reply