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Verilog HDL Program for Parallel In – Parallel Out Shift Register

Saturday, June 9th, 2012

Verilog HDL Program for Parallel In – Parallel Out Shift Register

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module pipo(sout,sin,clk);
    output [3:0]sout;
    input [3:0]sin;
    input clk;
    dff1 u1(sout[0],sin[0],clk);
    dff1 u2(sout[1],sin[1],clk);
    dff1 u3(sout[2],sin[2],clk);
    dff1 u4(sout[3],sin[3],clk);
endmodule
Simulated Waveform for Parallel In – Parallel Out Shift Register

Simulated Waveform for Parallel In – Parallel Out Shift Register

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