Verilog HDL Program for JK flip flop using RS flip flop

VHDL Program for JK flip flop using RS flip flop.

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	module sr2jk(q,q1,j,k,clk);
	output q,q1;
	input j,k,clk;
	and1 u1(w,j,q1);
	inv u4(k1,k);
	and1 u2(x,k1,q);
	srff u3(q,q1,x,w,clk);
	endmodule
Simulated Waveform for JK flip flop using RS flip flop
Simulated Waveform for JK flip flop using RS flip flop

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