Verilog HDL Program for detecting whether a given number is Prime or not

Verilog HDL Program for detecting whether a given number is Prime or not.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
module primenum3(o,i);
    output o; input [10:0]i; integer k; reg o;
    always @(i)
    begin
    k=i;
    if(i[0]==1'b0)
       begin   o=1'b0; $display("not prime");  end
       else 
       begin
       if(k==3 | k==5 | k==7 | k==11 | k==13 | k==17 | k==19)
       begin  o=1'b1; $display("prime"); end
       else if(k%3==0 | k%5==0 | k%7==0 | k%11==0 | k%13==0 | k%17==0 | k%19==0)
       begin   o=1'b0;  $display("not prime");    end 
       else
       begin   o=1'b1;  $display("prime");        end
       end
        if(i==10'b00 | i==10'b010)
        begin o=1'b1; $display("prime");  end
     end
 endmodule
Simulated waveform for detecting whether a given number is Prime or not
Simulated waveform for detecting whether a given number is Prime or not

One Response to “Verilog HDL Program for detecting whether a given number is Prime or not”

Leave a Reply