Verilog HDL Program for D Flip Flop

Saturday, June 9th, 2012

A flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.

he D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change. The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line.

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module d(q,q1,d,c);
output q,q1;
 input d,c;
 reg q,q1;
	initial 
	   begin
		   q=1'b0; q1=1'b1;
	  end
	always @ (posedge c)
	   begin 
		 q=d;
		 q1= ~d;
	   end
endmodule
Simulated waveform for D Flip Flop

Simulated waveform for D Flip Flop

Author Name :
Ansten Lobo

Total : 1 Comment


One Response to “Verilog HDL Program for D Flip Flop”

  1. Pablo says:

    Hah, girl-speek … God knows how many times I walked into that trap! Good news is, after a colupe of arguments about that, you, the guy, should learn about that kind of stuff. Sweet photo, BTW! And yes, nice pedi!

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