Verilog HDL Program for Carry Save Adder

Verilog HDL Program for Carry Save Adder.

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module carrysave(s,c,a,b);
    output [3:0]s;
    output c;
    input [3:0]a,b;
    wire [2:0]c2,c0;
    fa u1(s[0],c0[0],a[0],b[0],1'b0);
    dff1 u2(c2[0],c0[0],clk);
    fa u3(s[1],c0[1],a[1],b[1],c2[0]);
    dff1 u4(c2[1],c0[1],clk);
    fa u5(s[2],c0[2],a[2],b[2],c2[1]);
    dff1 u6(c2[2],c0[2],clk);
    fa u7(s[3],c,a[3],b[3],c2[2]);
endmodule
Simulated waveform for Carry Save Adder
Simulated waveform for Carry Save Adder

6 Responses to “Verilog HDL Program for Carry Save Adder”

  1. Please send me verilog code for 8*8 booth encoder
    please send me as soon as possible

    Reply
  2. Anand Mohan

    HI Arun,
    could you please send the the full program, as the program given is not complete. Two modules are missing.
    Thanks

    Reply
  3. sudheer kumar

    sir, i need a verilog HDL code for ” DESIGN AND IMPLEMENTATION OF 32-BIT VEDIC MULTIPLIER ON FPGA”.

    Reply
  4. I want to know what does dff refer to in the carry save adder code and this is a code for how many bits.

    Reply

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