Verilog HDL Program for 3-8 DECODER USING 2-4 DECODER

A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. It is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines.

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module dec38(o,i);
    output [7:0]o;
    input [2:0]i;
    wire x;
    inv u1(x,i[2]);
    decoder24 u2(o[3:0],i[1],i[0],x);
    decoder24 u3(o[7:4],i[1],i[0],i[2]);
endmodule
Simulated waveform for 3-8 Decoder
Simulated waveform for 3-8 Decoder

2 Responses to “Verilog HDL Program for 3-8 DECODER USING 2-4 DECODER”

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