Verilog HDL

Verilog HDL Program for Serail In – Parallel Out Shift Register

Verilog HDL Program for Serail In – Parallel Out Shift Register. 1 2 3 4 5 6 7 8 module sipo(sout,sin,clk); output [3:0]sout; input sin,clk; dff2 u1(sout[0],sin,clk); dff2 u2(sout[1],sout[0],clk); dff2 u3(sout[2],sout[1],clk); dff2 u4(sout[3],sout[2],clk); endmodule


Verilog HDL Program for Parallel In – Parallel Out Shift Register

Verilog HDL Program for Parallel In – Parallel Out Shift Register 1 2 3 4 5 6 7 8 9 module pipo(sout,sin,clk); output [3:0]sout; input [3:0]sin; input clk; dff1 u1(sout[0],sin[0],clk); dff1 u2(sout[1],sin[1],clk); dff1 u3(sout[2],sin[2],clk); dff1 u4(sout[3],sin[3],clk); endmodule


Verilog HDL Program for Parallel In – Serial Out Shift Register

Verilog HDL Program for Parallel In – Serial Out Shift Register. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module piso1(sout,sin,clk); output sout; input [3:0]sin; input clk; wire [3:0]q; inv u1(p,sl); and1 u2(n,sin[1],p); and1 u3(r,sl,q[0]); or1 u4(s,n,r); and1 u5(t,sin[2],p); and1 u6(u,sl,q[1]); or1 […]


Verilog HDL Program for Serail In – Serial Out Shift Register

Verilog HDL Program for Serail In – Serial Out Shift Register. 1 2 3 4 5 6 7 8 module sipo(sout,sin,clk); output [3:0]sout; input sin,clk; dff2 u1(sout[0],sin,clk); dff2 u2(sout[1],sout[0],clk); dff2 u3(sout[2],sout[1],clk); dff2 u4(sout[3],sout[2],clk); endmodule


Verilog HDL Program for BCD to GRAY conversion

Verilog HDL Program for BCD to GRAY conversion. 1 2 3 4 5 6 7 8 9 10 11 module bcd2gray(o,i); output [2:0]o; input [2:0]i; reg [2:0]o; always @(i) begin o[2]=i[2]; o[1]=i[2]^i[1]; o[0]=i[1]^i[0]; end endmodule


Verilog HDL Program for T flip flop using RS flip flop

Verilog HDL Program for T flip flop using RS flip flop. 1 2 3 4 5 6 7 8 module sr2t(q,q1,t,clk); output q,q1; input t,clk; wire x,y; and1 u1(x,t,q1); and1 u2(y,t,q); srff u3(q,q1,y,x,clk); //srff u(q,q1,r,s,clk); endmodule


Verilog HDL Program for D flip flop using RS flip flop

Verilog HDL Program for D flip flop using RS flip flop. 1 2 3 4 5 6 7 module sr2d(q,q1,d,clk); output q,q1; input d,clk; wire x; inv u1(x,d); srff u2(q,q1,x,d,clk); //srff u(q,q1,r,s,clk); endmodule


Verilog HDL Program for JK flip flop using RS flip flop

VHDL Program for JK flip flop using RS flip flop. 1 2 3 4 5 6 7 8 module sr2jk(q,q1,j,k,clk); output q,q1; input j,k,clk; and1 u1(w,j,q1); inv u4(k1,k); and1 u2(x,k1,q); srff u3(q,q1,x,w,clk); endmodule


Verilog HDL Program for T Flip Flop

A flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and […]


Verilog HDL Program for D Flip Flop

A flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and […]