# Verilog HDL

## Verilog HDL Program for detecting whether a given number is Prime or not

Verilog HDL Program for detecting whether a given number is Prime or not. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 module primenum3(o,i); output o; input [10:0]i; integer k; reg o; always @(i) begin k=i; if(i[0]==1’b0) begin o=1’b0; \$display("not prime"); end else begin […]

## Verilog HDL Program for Random Number Generator

Verilog HDL Program for Random Number Generator. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 module tff(q,t,c); output q; input t,c; reg […]

## Verilog HDL Program for the function f=x>>3 + x<<4

Verilog HDL Program for the function f=x>>3 + x

## Verilog HDL Program for Carry Save Adder

Verilog HDL Program for Carry Save Adder. 1 2 3 4 5 6 7 8 9 10 11 12 13 module carrysave(s,c,a,b); output [3:0]s; output c; input [3:0]a,b; wire [2:0]c2,c0; fa u1(s[0],c0[0],a[0],b[0],1’b0); dff1 u2(c2[0],c0[0],clk); fa u3(s[1],c0[1],a[1],b[1],c2[0]); dff1 u4(c2[1],c0[1],clk); fa u5(s[2],c0[2],a[2],b[2],c2[1]); dff1 u6(c2[2],c0[2],clk); fa u7(s[3],c,a[3],b[3],c2[2]); endmodule

## Verilog HDL Program for Counting Number of 1’s in a Vector

Verilog HDL Program for Counting Number of 1’s in a Vector. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module count1(o1,o0,i); // 4-bit vector output [2:0]o1,o0; // o1: Number of 1’s in vector, o0: Number of 0’s in vector input [3:0]i; wire [2:0]o; wire [3:1]c; […]

## Verilog HDL Program for Serial Parallel Multiplier

Verilog HDL Program for Serial Parallel Multiplier. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 module spm(s,m,q); output [7:0]s; input [3:0]m,q; and1 u1(s[0],m[0],q[0]); and1 u2(s1,m[0],q[1]); and1 u3(s2,m[0],q[2]); and1 u4(s3,m[0],q[3]); and1 u5(s4,m[1],q[0]); and1 […]

## Verilog HDL Program for Decade Counter

Verilog HDL Program for Decade Counter. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 module mod10(qo,clk); output [3:0]qo; input clk; inv u1(qc,q3); inv u2(qb,q1); inv u3(qa,q0); and1 u4(j3,q1,q0,q2); assign k3=q0; and1 u5(k2,q1,q0); assign j2=k2; and1 u6(j1,qc,q0); assign k1=q0; assign j0=1’b1; assign k0=1’b1; jk1 […]

## Verilog HDL Program for Mod-13 Counter

Verilog HDL Program for Mod-13 Counter. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 module mod13(qo,clk); output [3:0]qo; input clk; inv u1 (qd,q3); inv u2(qc,q2); and1 u3 (a,q1,q0,q2); and1 u4(b,q3,q2); or1 u5(t3,a,b); and1 u6(c,q1,q0); and1 u7(d,q3,q2); or1 u8(t2,c,d); assign t1=q0; or1 u9(t0,qd,qc); tff u10(qo[0],t0,clk); […]

## Verilog HDL Program for Johnson Counter

Verilog HDL Program for Johnson Counter. 1 2 3 4 5 6 7 8 9 module johnson(q,clk); output [3:0]q; input clk; not (qc,q[0]); dff u1(q[3],qc,clk); dff1 u2(q[2],q[3],clk); dff1 u3(q[1],q[2],clk); dff1 u4(q[0],q[1],clk); endmodule

## Verilog HDL Program for Ring Counter

Verilog HDL Program for Ring Counter. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 module dff(q,d,c); output q; input d,c; reg q; initial q=1’b1; always @ (posedge c) q=d; endmodule   module dff1(q,d,clk); output q; […]

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