Digital Electronincs

Verilog HDL Program for J K Flip Flop

A flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and […]


Verilog HDL Program for R-S Flip Flops

A flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and […]


Verilog HDL Program for BCD Adder using Parallel Adder

VHDL Program for BCD Adder using Parallel Adder. 1 2 3 4 5 6 7 8 9 10 11 12 13 module bcdas(s,c,a,b); output [3:0]s; output c; input [3:0]a,b; wire [3:0]x; wire z,y,co,c1,k; parad4 u1(x,c1,a,b); and1 u2(y,x[3],x[2]); and1 u3(z,x[1],x[3]); or1 u4(k,z,y); or1 u5(c,k,c1); parad4 u6(s,co,x,{1’b0,c,c,1’b0}); endmodule


Verilog HDL Program for 2X1 Multiplexer

a multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output. Multiplexers are mainly used to increase the […]


Verilog HDL Program for 3-8 ENCODER

An encoder is a device, circuit, transducer, software program, algorithm or person that converts information from one format or code to another, for the purposes of standardization, speed, secrecy, security, or saving space by shrinking size. 1 2 3 4 5 6 7 8 9 10 11 12 13 module encoder83(o,i); output [2:0]o; input [7:0]i; […]


Verilog HDL Program for 3-8 DECODER USING 2-4 DECODER

A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. It is a combinational circuit that converts binary information from n input lines to a maximum of […]


Verilog HDL program for 2 – 4 Decoder

A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. It is a combinational circuit that converts binary information from n input lines to a maximum of […]


Verilog HDL program for 4-BIT Parallel Adder

A 4 bit binary parallel adder can be formed by cascading four full adder units. The carry of each stage is connected to the next unit as the carry in (That is the third input). 1 2 3 4 5 6 7 8 9 10 module parad4(a,c,p,q); output [3:0]a; output c; input [3:0]p,q; wire c1,c2,c3; […]


Verilog HDL Program for FULL ADDER

A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in from the next less significant stage. The full-adder is usually a […]


Verilog HDL Program for HALF ADDER

The half adder adds two one-bit binary numbers A and B. It has two outputs, S and C (the value theoretically carried on to the next addition); the final sum is 2C + S. The simplest half-adder design, pictured on below, incorporates an XOR gate for S and an AND gate for C. With the […]